1. Field of the Invention
This invention relates to insulated gate field effect transistors (IGFET) and metal oxide semiconductor field effect transistors (MOSFET), in particular. Still more particularly, this invention relates to metal nitride oxide semiconductor (MNOS) transistors, most commonly employed as nonvolatile memory transistors.
2. Description of the Prior Art
Nonvolatile semiconductor memory transistor systems are known which typically employ large scale integration (LSI) or very large scale integration (VLSI) arrays of individual nonvolatile MOSFET elements with suitable interconnections to function as multi-bit storage devices. Each nonvolatile MOSFET element typically comprises a semiconductor substrate material of a first conductivity type, a pair of source and drain diffusion regions of opposite conductivity type from the substrate material and which are separated by an interstitial portion of the substrate material, an overlying dielectric oxide layer with minimum thickness in the region overlying the interstitial substrate portion, a layer of a different dielectric material over the oxide layer, and a gate electrode metallization or polysilicon layer overlying the dielectric material. In addition, an ohmic contact is provided for each diffusion region.
The nonvolatile MOSFET element above is most commonly implemented as the so-called MNOS transistor, which refers to the layers of the device in descending sequence, namely metal-nitride-oxide-semiconductor. The MNOS element can be operated as a two-state memory device by virtue of the variable threshold switching property exhibited by devices of this type. In a conventional field effect transistor, the threshold voltage which must be applied between the gate and the source electrodes to cause current conduction between the drain and the source electrodes is fixed. In MNOS devices, on the other hand, this threshold voltage can be altered by applying a relatively large potential difference across the gate dielectric. The threshold voltage may be altered back to a different level by applying a relatively large potential difference of opposite polarity across the gate dielectric. If the two different threshold voltages are well defined and of sufficiently different magnitude, an MNOS device may be operated as a bistable (binary) memory device by arbitrarily assigning one and zero values to the different threshold voltages, selectively altering the threshold voltage and subsequently interrogating the MNOS device with a voltage whose magnitude lies between the two different threshold voltages while sensing the source-to-drain current or voltage. The application of the relatively large potential difference across the gate dielectric causes charge carriers, either holes or electrons, to tunnel to the interface between the oxide layer and the nitride layer. The presence of these trapped charge carriers determines the threshold voltage level in the MNOS device.
The MNOS memory devices have been fabricated for use as bistable memory elements; and, while this MNOS implementation has many advantages, the performance of the early configurations of such devices was not found to be entirely satisfactory. One of the chief reasons for the unsatisfactory performance of these early variable threshold MNOS memory devices was the lack of predictability of the two different threshold voltages noted above. In the ideal case, the gate voltage-drain current characteristic of the device would consist of a pair of highly linear curves with very steep slopes and separated by a sufficient range of voltage in order that a range of gate voltages would exist which would cause the device to conduct heavily only if the device had been previously placed in the lower voltage threshold. The early devices did not approach the ideal case, however, and exhibited parasitic effects which result in gate voltage-drain current characteristics which varied between individual elements on a chip, and also varied from chip to chip in an unpredictable manner. These parasitic gate voltage-drain current characteristics were such that in either state the device could conduct heavily by applying the same interrogating gate voltage of a given magnitude. In other words, application of a given interrogation voltage to one of the early MNOS devices with this parasitic characteristic would not necessarily cause the device to conduct heavily in only the lower threshold state.
The apparent reason for this parasitic behavior of the early devices appeared to reside in the geometry required to produce an operable nonvolatile MNOS device. As noted above, such a device has an overlying oxide layer of minimum thickness in the region overlying an interstitial exposed portion of the substrate material which separates the two diffusion regions, with the oxide being covered by a layer of different dielectric material, which in turn is covered by a metallization layer in most usages. The field oxide layer elsewhere has a substantially uniform thickness many orders of magnitude greater than the minimum thickness beneath the gate electrode. Between the thick oxide region and the thin oxide region, there exists a transition region commonly termed a "sidewalk." This sidewalk region also functions as an MNOS device with gradually increasing oxide thickness. When the MNOS memory region, the thin oxide region, is switched between high and low threshold voltages, this transition region is switched to a threshold voltage somewhere between the high and low values of the main memory region. Thus, when the main channel is set at high threshold voltage, this transition region may be conducting at voltages lying below the high threshold voltage. Schematically the equivalent device would comprise a single MNOS memory element and two flanking MNOS devices with the source drain and gate elements coupled in parallel.
Many efforts have been made to solve this parasitic problem. Once such attempt has been to broaden the gate region in a direction perpendicular to the line separating the diffusion regions in order that the thin oxide gate region extends beyond the overlying gate electrode metallization layer. This solution introduces an additional problem due to the fringing electric field from the gate, termed the floating gate problem, in which charges tend to acumulate around the edge of the nitride insulation overlying the gate region with the result that the device rapidly degenerates into a different type of parasitic device exhibiting substantially the same parasitic behavior as noted above.
Another proposed solution has been the provision of a heavy ion-implantation region in the gate region which extends beyond the edges of the overlying gate electrode metallization layer in the direction noted above. These prior art ion-implantation techniques have exclusively dealt with relatively high energy ion-implantations which affect either the oxide layer or the underlying substrate. While this particular solution has been found to raise the threshold voltage of the regions adjacent the gate metallization layer beyond the high threshold voltage of the variable threshold MNOS device, the prior art implantation step is relatively difficult to perform in a controlled manner and inordinately lengthens the manufacturing process. An alternate variation of this solution has been the provision of a pair of independent blocking diffusion regions extending beyond opposite edges of the gate electrode metallization layer in the direction noted above and also partially into the gate region. This alternate solution, however, suffers from the same limitations as those noted above in that it requires additional processing steps, which increase the cost and the probability of error in manufacturing devices of this type.
Still another proposed solution has been to combat the sidewalk leakage by a variety of clever geometries involving different oxide thicknesses and varying overlaps thereof by the nitride and metallization layers. One such device is disclosed in U.S. Pat. No. 4,063,267 issued Dec. 13, 1977 to Yukun Hsia and assigned to the assignee of the present invention. While the more complex devices of this sort function properly when fabricated by the rather rigorous and complicated steps necessary for their implementation, this implementation has tended to be quite difficult. Additionally, with the increased complexity, additional space is required for each device. This is necessary because of invariant design rules. This is an obvious disadvantage given the larger considerations pointed towards increasingly smaller devices.